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Preliminary Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change.
M02140
Low Power 3.3 Volt Limiting Amplifier For Applications to 12.5 Gbps Low Power 3.3 Volt Limiting Amplifier
The M02140 is an integrated high-gain limiting amplifier intended for high-speed fiber optic based communications. Placed following the photodetector and transimpedance amplifier, the limiting amplifier provides the necessary gain to ensure full CML output swing even at its minimum input sensitivity. Capable of operating over a very wide frequency range, the M02140 supports data and telecom applications up to 12.5 Gbps. The M02140 includes an analog RSSI output and a programmable signal level detector allowing the user to set the threshold at which the loss of signal logic output is enabled.
Applications
* * * * STM-64/OC-192 SDH/SONET SDH/SONET with single or double FEC 10G Ethernet 10G Fiber Channel
Features
* * * * * * * * * * M02140 wide dynamic range with typical 5.5 mV input sensitivity at 10.3 Gbps Received Signal Strength Indicator (RSSI) Programmable input signal level detect Fully differential CML data outputs with typical 23 ps rise and fall time Wide -40 to +85 C operating temperature range Operates with +3.3 V supply Supply current typically 54 mA Programmable output amplitude (default 400 mVpp differential) On-chip DC offset cancellation circuit, no external capacitors needed
Typical Applications Diagram
RAMPSET +3.3 V VCC +3.3 V 50 DP IN TIA Photodiode D INN CMOS Buffer Limiting Amplifier CML Buffer DOUTN PWDN LOS AC or DC Coupled Level Detector Threshold Setting Circuit RSSI LOSSET AC or DC Coupled Comparator Biasing I REF ST 12.1 k 50 AMPSET Amplitude 50 Control
50 DOUTP
Clock Data Recovery Unit
RLOSSET
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M02140 Data Sheet
Ordering Information
Part Number Package Operating Temperature
-40 C to 85 C
M02140-XX
24 pin MLF package
Note: xx represents the revision number. Please contact your local sales office for correct digits.
Revision History
Revision
E D C B A
Level
Preliminary Preliminary Preliminary Preliminary Preliminary
Date
September 2004 June 2004 January 2004
ASIC Revision
Revised document layout. Update LOS specifications. Reformatted for new template.
Description
Initial Release.
Typical Eye Diagram
Pin Configuration
PDWN
RSSI
LOS
IREF
24
N/C AMPSET GND DOUTN
1
N/C 19 18
ST
N/C GND GND DIN N DIN P
Conditions
10 mVpp differential input 10.3 Gbps, Pattern 2 23 -1 LOW output CML level Time 20 ps/Div. Amp 50 mV/Div
DOUT P N/C 6 13
N/C
7
12 LOSSET VCC N/C GND N/C
Scale
2
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N/C
02140-DSH-001-E
1.0 Product Specification
1.1
Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reliable operation at these extremes for any length of time is not implied. Table 1-1. Symbol VCC TA TSTG DOUTP, DOUTN DINP, DINN AMPSET LOSSET PWDN IREF RSSI I(ST) I(LOS) Absolute Maximum Ratings Parameter Power supply voltage (VCC - GND) Operating ambient temperature Storage temperature Output pins voltage Data input pins voltage Output amplitude setting pin voltage Signal detect threshold setting pin voltage Output enable pin voltage Current into Reference input RSSI pin voltage Current into Status pin Current into Loss Of Signal pin Rating -0.4 to +4.0 -40 to +85 -65 to +150 VCC - 0.4 to VCC + 0.4 VCC - 0.32 to VCC + 0.32 GND to +0.1 GND to +3.6 GND to +3.6 + 0 to -120 +1 to +3.6 +1500 to -100 +1500 to -100 Units V C C V V V V V A V A A
1.2
Table 1-2.
Recommended Operating Conditions
Recommended Operating Conditions Parameter Rating 3.3 5% -40 to +85 Units V C
Power supply (VCC - GND) Operating ambient temperature
Note: The package bottom must be adequately grounded to ensure correct thermal and electrical performance. It is recommended that a minimum of four vias be used with 0.3 to 0.33 mm diameter and 1.0 to 1.2 mm pitch to contact a ground plane.
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M02140 Data Sheet
1.3
DC Characteristics
(VCC = +3.3V 5%, TA = -40C to +85C, Outputs connected to a 50 load to VCC, unless otherwise noted).
Typical values are at VCC = 3.3 V and TA = 25 C, unless otherwise noted. Table 1-3. Symbol ICC DC Characteristics Parameter Supply current (ICC) Conditions 400 mVpp differential output amplitude 800 mVpp differential output amplitude 400 mVpp differential output amplitude, settled value, (RAMPSET = 0 , DIN 20 mVpp) 800 mVpp differential output amplitude, settled value, (RAMPSET = 887 , DIN 20 mVpp) 400 mVpp differential output amplitude, settled value, (RAMPSET = 0 , DIN 20 mVpp) 800 mVpp differential output amplitude, settled value, (RAMPSET = 887 , DIN 20 mVpp) Minimum - - VCC - 0.22 Typical 54 61 Maximum 70 75 Units mA mA V
VCC - 0.2 VCC - 0.18
DataOutL
Single-ended CML output low
VCC - 0.44
VCC - 0.4 VCC - 0.36
V
VCC - 0.02
-
VCC
V
DataOutH
Single-ended CML output high
VCC - 0.04
-
VCC
V
VIN(CM) RIN(DIFF)
Data input common mode voltage Input swing between VIN(MIN) and range VIN(MAX) (see Table 1.4) Data input differential resistance
VCC - 0.250 85 85
- 100 100 - -
VCC 115 115 - 0.4 VCC 0.8
V V V V V
ZOUT(DIFF) Data output differential impedance VOH VOL VIH VIL ST/LOS output HIGH voltage ST/LOS output LOW voltage PWDN input HIGH voltage PWDN input LOW voltage 4.7 k to VCC 4.7 k to VCC
2.4
2.0 0
- -
4
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Product Specification
1.4
AC Characteristics
(VCC = +3.3V 5%, TA = -40C to +85C, input bit rate = 10.3 Gbps, 231 - 1 PRBS, unless otherwise noted). Typical values are at VCC = 3.3 V and TA = 25 C, unless otherwise noted. Table 1-4. Symbol AC Characteristics Parameter Conditions BER <10-10, differential input BER <10-10, single-ended input VIN(MIN) Input Sensitivity (1, 2, 3) BER <10-12, differential input BER <10-12, 12.5 Gbps, differential input VIN(MAX) EN Input Overload
(1, 2)
Minimum - - - - 1000 500 - - - - - - - - - 10 2 8 -
Typical 5.5 - 6.5 9 - - 450 0.8 0.8 3.3 3.7 1.3 23 28 50 - 4.5 (6) 12.5 21
Maximum Units 7 7 8 - - - mVPP mVPP mVPP mVPP mVPP mVPP VRMS 1.2 1.2 10 12 5 30 40 75 100 7.5 - 32 psRMS psRMS psPP psPP ps ps ps kHz mVPP dB mVPP mVPP
BER <10-10, differential input BER <10-10, single-ended input Measured differentially 20 mVPP differential input, alternating 1-0 pattern 12.5 Gbps, 20 mVPP differential input, alternating 1-0 pattern 20 mVPP differential input 20 mVPP differential input, 12.5 Gbps Alternating 1-0 pattern at 2488 Mbps(4) 400 mVpp differential output amplitude, (RAMPSET = 0 ) (5) 800 mVpp differential output amplitude, (RAMPSET = 887 ) (5)
Input referred noise
RJ
Random Jitter
DJ DCD
Deterministic Jitter (includes DCD) Duty Cycle Distortion
tr, tf
Data outputs rise and fall time (input > 20 mVPP differential)
fL LOSTH VHYST ASSERTLOW DEASSERTLOW
Small signal -3 dB low frequency Excluding AC coupling capacitors cut off LOS programmable threshold range LOS hysteresis Low Input RLOS LOS Assert threshold Low Input RLOS LOS De-Assert threshold Differential input Electrical LOS threshold across programmable threshold range RLOS = 4.99 k, differential input RLOS = 4.99 k, differential input
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M02140 Data Sheet
Table 1-4. Symbol ASSERTMED DEASSERTMED ASSERTHI DEASSERTHI TLOS_ON
AC Characteristics Parameter Medium Input RLOS LOS Assert threshold Medium Input RLOS LOS DeAssert threshold High Input RLOS LOS Assert threshold High Input RLOS LOS De-Assert threshold Conditions RLOS = 4.75 k, differential input RLOS = 4.75 k, differential input RLOS = 4.02 k, differential input RLOS = 4.02 k, differential input Minimum 16 - 48 - Typical 25 41 75 125 13.5 (7) Maximum Units - 65 - 190 mVPP mVPP mVPP mVPP s
LOS assert time after 1 Vpp input signal Time from LOS state until LOS is or smaller is turned off; LOS assert level asserted (ST de-asserted) set to 10 mV Time from non-LOS state until LOS is de-asserted (ST asserted) LOS de-assert time after input crosses LOS de-assert level; LOS de-assert level set to 20 mV with applied input signal of 30 mVpp or greater
-
80
TLOS_OFF
-
7 (8)
80
s
Notes: 1. 5.5 - 1000 mVpp differential input translates to 2.75 - 500 mVpp for each single-ended input. See Figure 1-1. 2. When driven with a single-ended input, the unused input is DC-coupled through 50 to the common mode level of the driven input. See Figure 1-1. 3. There is no difference in performance using a 223 - 1 PRBS versus a 231 - 1 PRBS. 4. Measured as [(pulse width of a one) - (pulse width of a zero)]/2. Pulse width measured at 50% points. 5. The rise and fall times are using the 20% to 80% thresholds at each output. The output is DC-coupled into 50 to VCC. 6. This corresponds to 2.25 dB optical. 7. With VIN_DIFF = 1 Vpp, typical times decrease as VIN_DIFF decreases. 8. With VIN_DIFF = 30 mVpp, typical times decrease as VIN_DIFF increases.
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Product Specification
Figure 1-1.
Data Input Requirements
Differential Input
DINP 2.75 - 500 mV DINN
VIN(DIFF)
5.5 - 1000 mV
Single-ended Input (1)
DINP or DINN Unused Input 5.5 - 500 mV
VIN(DIFF)
5.5 - 500 mV
Note: 1. Unused input AC-coupled through 50 to VCC when used input is AC-coupled to TIA; Unused input DC-coupled through 50 to the common mode level of TIA output when the used input is DC-coupled to the TIA
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2.0 Pin Definitions
Table 2-1. MLF Pin Number 1 2 3 4 5 6, 7, 8 9 10 11 12, 13 14 15 16, 17 18, 19 20 21 22 23 24 EP
Pin Descriptions Name N/C AMPSET GND DOUTN DOUTP N/C VCC LOSSET GND N/C DINP DINN GND N/C IREF PWDN LOS ST RSSI Exposed Paddle Function Not connected. (Not internally bonded, can be connected to any DC potential including ground) Enables setting of output voltage swing from 400 mVpp differential to 800 mVpp differential using an external 1% resistor (RAMPSET) to ground Ground Inverting differential data output. CML output internally terminated 50 to VCC Non-inverting differential data output. CML output internally terminated 50 to VCC Not connected. (Not internally bonded, can be connected to any DC potential including ground) Positive supply Loss of signal threshold setting input. User programmed with 1% resistor (RLOS) to VCC Ground Not connected. (Not internally bonded, can be connected to any DC potential including ground) Non-inverting data input. Internally terminated 50 to VCC Inverting data input. Internally terminated 50 to VCC Ground Not connected. (Not internally bonded, can be connected to any DC potential including ground) Reference current termination. Must be connected to ground through an external 12.1 k, 1% resistor (RREF). This connection generates an on-chip reference current CMOS compatible logic input. When high, the output stage current is switched off, this will make DOUTP and DOUTN both equal to VCC. Data outputs are enabled when PWDN is low or floating Loss of Signal Indicator. Asserted when input signal levels falls below threshold established at LOSSET. May be externally connected to the PWDN pin to enable the automatic jam function Input signal level status. Logical inverse of LOS. This output is LOW when the input signal is below the threshold set at LOSSET. This is an open drain output with an internal 100 k pull-up Received signal strength indicator. The output amplitude is proportional to the received input signal level Package backside. Must be conductively connected to ground
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M02140 Data Sheet
Figure 2-1.
24 Pin (4 x 4mm) MLF top view
PDWN RSSI
LOS
IREF
24
N/C AMPSET GND DOUTN DOUT P N/C
1
N/C 19 18
ST
N/C GND GND DIN N DIN P
6
13
N/C
7 VCC LOSSET N/C N/C GND
12 N/C
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3.0 Functional Description
3.1
Overview
The M02140 is a high-gain limiting amplifier for applications up to 12.5 Gbps, and incorporates a limiting amplifier, a CML buffer and an input signal level detection circuit. The M02140 also features a fully integrated DC-offset cancellation loop that does not require any external components. The user is provided with the flexibility to set the output amplitude levels and the signal detect threshold. Optional output buffer disable (squelch/jam) can be implemented using the PWDN input. Figure 3-1. M02140 Block Diagram
VCC
AMPSET
50
50
Amplitude Control
50
50
D D
P IN N IN
Limiting Amplifier
CML Buffer
DOUTP DOUTN CMOS Buffer PWDN
Level Detector Threshold Setting Circuit RSSI LOS
ST Comparator Biasing LOS
I
REF
SET
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M02140 Data Sheet
3.2
3.2.1
General Description
Inputs
The data inputs are internally biased to VCC via 50 resistors, and may be AC or DC-coupled. Note that if the inputs are AC-coupled, the coupling capacitor should be of sufficient value to pass the lowest frequencies of interest, bearing in mind the number of consecutive identical bits, and the input resistance (It is recommended a capacitor of 2 to 10 nF be used). The coupling capacitor should also be of sufficient quality as to pass the high frequency content of the input data stream.
3.2.2
DC Offset Compensation
The M02140 contains internal DC feedback requiring no external components to remove the effects of DC offsets and to act as a DC auto-zero circuit. This circuit is configured such that the feedback is effective only at frequencies well below the lowest frequency of interest. The low frequency cut off typically is less than 50 kHz.
3.2.3
Outputs
The basic output configuration is as shown in Figure 3-2. The external resistor RAMPSET controls the value of ITAIL. The output swing is linearly proportional to the value of RAMPSET. It is possible to set the output voltage swing linearly between 400 mVpp differential and 800 mVpp differential, when the outputs are properly terminated. See the applications information section for further details on setting the output swing amplitude. Figure 3-2. Data Outputs
V CC
M02140 RLOAD
V CC
RLOAD
ROUT
ROUT
DOUTP
DOUTN ROUT = 50 RLOAD = 50
ITAIL
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Functional Description
3.2.4
Received Signal Strength Indicator (RSSI)
The RSSI output voltage is proportional to the log of the input signal amplitude as shown in Figure 3-3 (the RSSI output voltage is linearly proportional to the Optical Modulation Amplitude (OMA)). An external 4.7 nF capacitor must be connected from the RSSI output to VCC as shown in Figure 3-4. The capacitor integrates the RSSI output and also sets the loss of signal reaction time. The RSSI voltage is compared with a selectable reference to determine loss of signal as described in the next section. Figure 3-3. RSSI Output
V CC 766 4.7nF
M02140
V RSSI RSSI Idetected 20 pF
Figure 3-4.
0.75 0.8 0.85 VCC - V RS SI Voltage (V) 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1
RSSI Transfer Function
2.55
Conditions: 23 10.3 Gbps, 2 -1 Vcc = 3.3V, Temp = 25C
2.50 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 1000 V RSSI (V) at V CC = 3.3V
11
10 Differential Input Level (mV pp) 100
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M02140 Data Sheet
3.2.5
Loss of Signal (LOS)
The M02140 features input signal level detection over an extended range. Using an external resistor, RLOS, between pin LOSSET and VCC, the user can program the input signal threshold. The signal detect status is indicated on the LOS and ST open-drain output pins shown in Figure 3-5. These two pins are inverses of each other: the LOS signal is active when the signal is below the threshold value, ST is active when the signal is above the threshold value. The signal detection circuitry has the equivalent of 4.5dB (typical) electrical hysteresis. Figure 3-5. LOS and ST Outputs
VCC M02140
100 ST or LOS
RLOS establishes a threshold voltage at the LOSSET pin as shown in Figure 3-6. The input signal develops a voltage at the RSSI pin as shown in Figure 3-4. As described in the RSSI section, this voltage is proportional to the input signal peak to peak value. The voltage at LOSSET is internally compared to the voltage at the RSSI (V(RSSI)) pin. When the voltage at V(RSSI) is less than V(LOSSET), LOS is asserted (ST de-asserted) and will stay asserted until the input signal level increases by a predefined amount of hysteresis. When the input level increases by more than this hysteresis, LOS is de-asserted (ST asserted). See the applications section for the selection or RLOS. Figure 3-6. LOSset Input
V CC M02140
RLOS V LOSSET LOS SET 204 A
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Functional Description
3.2.6
Squelch Function (Jam) using PWDN
When asserted, the active high power down (PWDN) pin forces the outputs to a high state. This ensures that no data is propagated through the system. The loss of signal detection circuit can be used to automatically force the data outputs to a high state when the input signal falls below the threshold. The function is normally used to allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the data outputs toggling due to noise when there is no signal present ("squelch"). In order to implement this function, LOS should be connected to the PWDN pin shown in Figure 3-7, thus forcing the data outputs to VCC when the signal falls below the threshold. Note that LOSSET can be left open if the loss of signal detector function is not required. In this case LOS would be low. Figure 3-7. Power Down (PWDN)
VCC
PWDN
320
M02140
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M02140 Data Sheet
3.2.7
Bias Generation
The M02140 contains an accurate on-chip bias circuit requiring an external 12.1 k 1% resistor, RREF, from pin IREF to ground to define an on-chip reference current. Figure 3-8. Reference Current Connection
VCC
103 A 1.23V
+ 1.23V IREF
RREF 12.1 k
M02140
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4.0 Applications Information
4.1
Setting the Output Swing Level
The output circuit is shown in Figure 3-2. It is basically a differential pair with a tail current of ITAIL. The load of the differential pair is formed by the parallel combination of ROUT and RLOAD for high frequencies where the output ACcoupling capacitor can be considered as a short circuit (50 || 50 = 25 ). The single-ended output voltage swing is given by EQ.1: VPP-SE = ITAIL x (ROUT || RLOAD)
EQ. 1
The required minimum voltage swing sets ITAIL and ITAIL determines the output power consumption. The minimum voltage swing depends on the application. Therefore, M02140 provides the user the flexibility to optimize the voltage swing and the output power consumption in his own application by setting ITAIL using an external resistor (RAMPSET) shown in Figure 4-1. To select the required swing, use the following equation (EQ.2): ITAIL = 8 mA + (RAMPSET x 9.0 x10-3) mA
EQ. 2
Figure 4-1.
AMPset
VCC 103 A VAMPSET 844 AMPSET
RAMPSET
M02140
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M02140 Data Sheet
The minimum ITAIL is 8mA and occurs when the AMPSET pin is directly connected to ground. The resulting voltage swing is 200 mVpp, single-ended (= 8 mA x 25 ). This is sufficient for most applications. If it is necessary, the voltage swing can be increased at the expense of the power consumption by connecting an external resistor RAMPSET between the AMPSET pin and ground. The value of RAMPSET can be calculated from EQ.2. A resistor of 887 results in 16 mA tail current which delivers a voltage swing of 400 mVpp, single-ended (16 mA x 25 ).
4.2
Setting the Signal Detect Level
Using Figure 4-2, the value for RLOS is chosen to set the LOS threshold at the desired value. The resulting hysteresis is also shown in Figure 4-2. Three example RLOS resistor values are given in Table 7. From Figure 4-2, it is apparent that small variations in RLOS cause significant variation in the LOS threshold level, particularly for low input signal levels. This is because of the logarithmic relationship between the RSSI voltage and the input signal level. It is recommended that a 1% resistor be used for RLOS and that allowance is provided for LOS variation, particularly when the LOS threshold is near the sensitivity limit of the M02140. Table 4-1. RLOS Resistor Values RLOS (k) (nearest 1% value) 4.99 4.64 4.22 4.02
LOS Assert Threshold VIN (mV pp) differential 10 20 50 75 Figure 4-2.
140
Loss of Signal Characteristic
120
Conditions: 10.3 Gbps, 223-1 Vcc = 3.3V, Temp = 25C
Threshold Level (mVpp diff)
100
80 LOS De-assert 60 LOS Assert 40 Optical Hysteresis = 10*log10{De-assert/Assert}
20
0 3.9 4.1 4.3 4.5 RLOS (k) 4.7 4.9
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5.0 Package Specification
Figure 5-1.
Package Information
Note: View is for a 20 pin package. All dimensions in the tables apply for the 24 pin package
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(c) 2004, Mindspeed TechnologiesTM, Inc. All rights reserved. Information in this document is provided in connection with Mindspeed TechnologiesTM ("MindspeedTM") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed's Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale.
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M02140 Data Sheet
www.mindspeed.com General Information: U.S. and Canada: (800) 854-8099 International: (949) 483-6996 Headquarters - Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA. 92660
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